Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC applications

Abstract

In this paper, by using neural network, we proposed the methodology of optimizing the Fully-Depleted (FD) Silicon On Insulator (SOI) FET structures having the best DC performance (on/off current ratios), which are suitable for 14-nm node (70-nm Gate Pitch) SoC and sequential 3DIC applications. Utilization of FDSOI in sequential 3DIC makes the device design complex, hence fast and efficient design methodology is needed. By modeling the neural network, the behaviors of 14-nm node FDSOI FETs were learned accurately and the desired structures were suggested in terms of on/off current ratios of HP, LOP, and LSTP. These optimized structures were secured within the range where conventional FDSOI FET were designed. The neural network based methodology was rapidly able to provide the low cost and optimized device design solution in the fickle 3DIC environment, which should integrate various semiconductor technology. © 2020 IEEE.