DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, TH | - |
dc.contributor.author | Kim, YH | - |
dc.date.accessioned | 2015-06-25T02:01:18Z | - |
dc.date.available | 2015-06-25T02:01:18Z | - |
dc.date.created | 2009-08-06 | - |
dc.date.issued | 1999-03 | - |
dc.identifier.issn | 0916-8508 | - |
dc.identifier.other | 2015-OAK-0000000672 | en_US |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/10304 | - |
dc.description.abstract | This paper presents a heuristic algorithm that minimizes the delay of the given circuit through a two-pass cell selection in cell-based design. First,we introduce a new graph, called candidate web, which conveniently represents all cell combinations available for the implementation of the given circuit. We, then, present an efficient method to obtain a tentative set of optimal cells, while estimating the delay of the longest path between each cell and the primary output on the candidate web. In this step, multiple cells are allowed to bind the same logic gate. Finally, we describe hopi the proposed approach actually selects the optimal cells from the tentative set, which would minimize the circuit delay. Experimental results on a set of benchmarks show that the proposed approach is effective and efficient in minimizing the delay of the given circuit. | - |
dc.description.statementofresponsibility | open | en_US |
dc.language | English | - |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION CO | - |
dc.relation.isPartOf | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | - |
dc.rights | BY_NC_ND | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/2.0/kr | en_US |
dc.title | DEMI: A delay minimization algorithm for cell-based digital VLSI design | - |
dc.type | Article | - |
dc.contributor.college | 전자전기공학과 | en_US |
dc.author.google | Kim, TH | en_US |
dc.author.google | Kim, YH | en_US |
dc.relation.volume | E82-A | en_US |
dc.relation.issue | 3 | en_US |
dc.relation.startpage | 504 | en_US |
dc.relation.lastpage | 511 | en_US |
dc.contributor.id | 10176127 | en_US |
dc.relation.journal | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | en_US |
dc.relation.index | SCI급, SCOPUS 등재논문 | en_US |
dc.relation.sci | SCIE | en_US |
dc.collections.name | Journal Papers | en_US |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E82-A, no.3, pp.504 - 511 | - |
dc.identifier.wosid | 000079373100016 | - |
dc.date.tcdate | 2019-01-01 | - |
dc.citation.endPage | 511 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 504 | - |
dc.citation.title | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | - |
dc.citation.volume | E82-A | - |
dc.contributor.affiliatedAuthor | Kim, YH | - |
dc.identifier.scopusid | 2-s2.0-0032634945 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 1 | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | delay minimization | - |
dc.subject.keywordAuthor | cell-based design | - |
dc.subject.keywordAuthor | critical path analysis | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Information Systems | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
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