Open Access System for Information Sharing

Login Library

 

Article
Cited 11 time in webofscience Cited 11 time in scopus
Metadata Downloads
Full metadata record
Files in This Item:
There are no files associated with this item.
DC FieldValueLanguage
dc.contributor.authorHA, MINHO-
dc.contributor.authorLEE, YOUNGJOO-
dc.contributor.authorMOON, SEUNGSIK-
dc.contributor.authorBYUN, YOUNGHOON-
dc.contributor.authorLEE, SUNG GU-
dc.date.accessioned2021-01-14T05:50:03Z-
dc.date.available2021-01-14T05:50:03Z-
dc.date.created2021-01-04-
dc.date.issued2021-01-
dc.identifier.issn0278-0070-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/104806-
dc.description.abstractIn order to effectively reduce buffer energy consumption, which constitutes a significant part of the total energy consumption in a convolutional neural network (CNN), it is useful to apply different amounts of energy conservation effort to the different levels of a CNN as the buffer energy to total energy usage ratios can differ quite substantially across the layers of a CNN. This article proposes layerwise buffer voltage scaling as an effective technique for reducing buffer access energy. Error-resilience analysis, including interlayer effects, conducted during design-time is used to determine the specific buffer supply voltage to be used for each layer of a CNN. Then these layer-specific buffer supply voltages are used in the CNN for image classification inference. Error injection experiments with three different types of CNN architectures show that, with this technique, the buffer access energy and overall system energy can be reduced by up to 68.41% and 33.68%, respectively, without sacrificing image classification accuracy.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.relation.isPartOfIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS-
dc.titleLayerwise Buffer Voltage Scaling for Energy-Efficient Convolutional Neural Network-
dc.typeArticle-
dc.identifier.doi10.1109/TCAD.2020.2992527-
dc.type.rimsART-
dc.identifier.bibliographicCitationIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.40, no.1, pp.1 - 10-
dc.identifier.wosid000604874900001-
dc.citation.endPage10-
dc.citation.number1-
dc.citation.startPage1-
dc.citation.titleIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS-
dc.citation.volume40-
dc.contributor.affiliatedAuthorHA, MINHO-
dc.contributor.affiliatedAuthorLEE, YOUNGJOO-
dc.contributor.affiliatedAuthorMOON, SEUNGSIK-
dc.contributor.affiliatedAuthorBYUN, YOUNGHOON-
dc.contributor.affiliatedAuthorLEE, SUNG GU-
dc.identifier.scopusid2-s2.0-85099019137-
dc.description.journalClass1-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.type.docTypeArticle-
dc.subject.keywordAuthorApproximate computing-
dc.subject.keywordAuthorconvolutional neural network (CNN)-
dc.subject.keywordAuthorenergy-efficient memory-
dc.subject.keywordAuthorerror resilience analysis-
dc.subject.keywordAuthorBit error rate-
dc.subject.keywordAuthorRandom access memory-
dc.subject.keywordAuthorSystem-on-chip-
dc.subject.keywordAuthorResilience-
dc.subject.keywordAuthorVoltage control-
dc.subject.keywordAuthorMoon-
dc.subject.keywordAuthorComputer architecture-
dc.relation.journalWebOfScienceCategoryComputer Science, Hardware & Architecture-
dc.relation.journalWebOfScienceCategoryComputer Science, Interdisciplinary Applications-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.description.journalRegisteredClassscopus-

qr_code

  • mendeley

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

Related Researcher

Researcher

이승구LEE, SUNG GU
Dept of Electrical Enginrg
Read more

Views & Downloads

Browse