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dc.contributor.authorPark, Yoonho-
dc.contributor.authorKang, Yesung-
dc.contributor.authorKim, Sunghoon-
dc.contributor.authorKwon, Eunji-
dc.contributor.authorKang, Seokhyeong-
dc.date.accessioned2021-06-01T08:04:46Z-
dc.date.available2021-06-01T08:04:46Z-
dc.date.created2021-03-10-
dc.date.issued2020-08-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/106075-
dc.description.abstractConvolutional neural networks (CNNs) require a huge amount of off-chip DRAM access, which accounts for most of its energy consumption. Compression of feature maps can reduce the energy consumption of DRAM access. However, previous compression methods show poor compression ratio if the feature maps are either extremely sparse or dense. To improve the compression ratio efficiently, we have exploited the spatial correlation and the distribution of non-zero activations in output feature maps. In this work, we propose a grid-based run-length compression (GRLC) and have implemented a hardware for the GRLC. Compared with a previous compression method [1], GRLC reduces 11% of the DRAM access and 5% of the energy consumption on average in VGG-16, ExtractionNet and ResNet-18.-
dc.languageEnglish-
dc.publisherAssociation for Computing Machinery-
dc.relation.isPartOf2020 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2020-
dc.relation.isPartOfACM International Conference Proceeding Series-
dc.titleGRLC: Grid-based run-length compression for energy-efficient CNN accelerator-
dc.typeConference-
dc.type.rimsCONF-
dc.identifier.bibliographicCitation2020 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2020-
dc.citation.conferenceDate2020-08-10-
dc.citation.conferencePlaceUS-
dc.citation.title2020 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2020-
dc.contributor.affiliatedAuthorKang, Seokhyeong-
dc.identifier.scopusid2-s2.0-85098243831-
dc.description.journalClass1-
dc.description.journalClass1-

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