Giga-sample Data Acquisition Method for High-speed DDR5 SDRAM

Abstract

We propose a data acquisition system that enables over-sampling of signals with an external high-speed clock, to overcome the unreliability of the existing data acquisition method that uses a DRAM memory clock, when applied to data rate fifth-generation synchronous dynamic random-Access memory [1]. We present a simple noise-modeling method and signal-recovery algorithm with a noise range where our algorithm behaves reliably at error rate < 10-6. In addition, we propose an entire data acquisition system architecture that uses a Xilinx FPGA VCU118 board.