DC Field | Value | Language |
---|---|---|
dc.contributor.author | Im, Jaekyung | - |
dc.contributor.author | Kang, Seokhyeong | - |
dc.date.accessioned | 2022-03-02T00:23:09Z | - |
dc.date.available | 2022-03-02T00:23:09Z | - |
dc.date.created | 2022-02-20 | - |
dc.date.issued | 2021-10-07 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/109684 | - |
dc.description.abstract | Chisel is a hardware design method that uses Scala programming language, and exploits many useful features of Scala like object-oriented programming and functional programming. By comparing two equivalent RISC-V core designs, one implemented using each hand-written Verilog code and one using Chisel, this paper compares manual Verilog coding and Chisel coding. The comparison metrics are source-code density, area of synthesized hardware, and RTL simulation run-Time. As a result, Chisel is proved to be more productive than Verilog. | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.relation.isPartOf | 18th International System-on-Chip Design Conference, ISOCC 2021 | - |
dc.relation.isPartOf | Proceedings - International SoC Design Conference 2021, ISOCC 2021 | - |
dc.title | Comparative Analysis between Verilog and Chisel in RISC-V Core Design and Verification | - |
dc.type | Conference | - |
dc.type.rims | CONF | - |
dc.identifier.bibliographicCitation | 18th International System-on-Chip Design Conference, ISOCC 2021, pp.59 - 60 | - |
dc.identifier.wosid | 000861550500030 | - |
dc.citation.conferenceDate | 2021-10-06 | - |
dc.citation.conferencePlace | KO | - |
dc.citation.endPage | 60 | - |
dc.citation.startPage | 59 | - |
dc.citation.title | 18th International System-on-Chip Design Conference, ISOCC 2021 | - |
dc.contributor.affiliatedAuthor | Kang, Seokhyeong | - |
dc.identifier.scopusid | 2-s2.0-85123370642 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
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