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dc.contributor.authorRIM, DONGYOUNG-
dc.contributor.authorLEE, YOUNGJOO-
dc.date.accessioned2022-03-03T05:41:01Z-
dc.date.available2022-03-03T05:41:01Z-
dc.date.created2022-03-03-
dc.date.issued2021-11-02-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/110210-
dc.description.abstractFor the given deep convolutional neural network (DCNN) models, in this work, we carefully evaluate systolic DNN accelerators associated with different array configurations. In order to find the optimal array structure in terms of the processing efficiency, the open-source evaluation framework is adopted for investigating the relationships between the network architecture and the hardware-level options. We also present the selection criteria of array structure that leads to the efficient accelerator designs.-
dc.languageEnglish-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.relation.isPartOf2021 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2021-
dc.relation.isPartOf2021 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2021-
dc.titlePerformance Evaluation of Systolic DCNN Accelerators-
dc.typeConference-
dc.type.rimsCONF-
dc.identifier.bibliographicCitation2021 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2021-
dc.identifier.wosid000766412700066-
dc.citation.conferenceDate2021-11-01-
dc.citation.conferencePlaceKO-
dc.citation.conferencePlaceSOUTH KOREA-
dc.citation.title2021 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2021-
dc.contributor.affiliatedAuthorRIM, DONGYOUNG-
dc.contributor.affiliatedAuthorLEE, YOUNGJOO-
dc.description.journalClass1-
dc.description.journalClass1-

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이영주LEE, YOUNGJOO
Dept of Electrical Enginrg
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