Low-complexity and low-latency SVC decoding architecture using modified MAP-SP algorithm
SCIE
SCOPUS
- Title
- Low-complexity and low-latency SVC decoding architecture using modified MAP-SP algorithm
- Authors
- SEUNGWOO, HONG; KAM, DONG YUN; YUN, SANGBU; JEONGWON, CHOE; LEE, NAMYOON; LEE, YOUNGJOO
- Date Issued
- 2022-04
- Publisher
- Institute of Electrical and Electronics Engineers
- Abstract
- The compressive sensing (CS) based sparse vector coding (SVC) method is one of the promising ways for the next-generation ultra-reliable and low-latency communications. In this paper, we present advanced algorithm-hardware co-optimization schemes for realizing a cost-effective SVC decoding architecture. The previous maximum a posteriori subspace pursuit (MAP-SP) algorithm is newly modified to relax the computational overheads by applying novel residual forwarding and LLR approximation schemes. A fully-pipelined parallel hardware is also developed to support the modified decoding algorithm, reducing the overall processing latency, especially at the support identification step. In addition, an advanced least-square-problem solver is presented by utilizing the parallel Cholesky decomposer design, further reducing the decoding latency with parallel updates of support values. The implementation results from a 22nm FinFET technology showed that the fully-optimized design is 9.6 times faster while improving the area efficiency by 12 times compared to the baseline realization.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/110308
- DOI
- 10.1109/TCSI.2021.3136222
- ISSN
- 1549-8328
- Article Type
- Article
- Citation
- IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 4, page. 1774 - 1787, 2022-04
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