A Study on Al/TiO2/Si Capacitor for Ultra High-k Gate Stack

Abstract

CMOS technology has continued to improve performance of device by scale-down. The device scaling scheme made the oxide thickness shrink as well as other parameters of the device. So, as a result of continued scaling, extremely thin oxide layer was developed, which causes direct tunneling. To prevent the leakage current caused by direct tunneling, high-k gate dielectric that is physically thick but maintains the same gate capacitance as SiO2 was required. In response to this requirement, since 45nm technology node, hafnium based oxide (HfO2) that has large permittivity and is compatible to conventional CMOS technology have been used. Due to further scaling, however, HfO2 also has reached scaling limitation and so much higher-k dielectric have been needed again. TiO2 is a good candidate for replacement material for HfO2 owing to its large dielectric constant (~ 80). However, TiO2 has a small energy band gap, which can make it show large leakage current. Because of this problem, before TiO2 can be used as a gate dielectric, its leakage current must be reduced. Therefore, the cause of its leakage current must be understood. In this study, Al/TiO2/Si, Metal/Insulator/Semiconductor (MIS), capacitors were fabricated so that their electrical properties could be quantified. TiO2 was deposited by sputtering on prepared n-doped silicon wafer, then rapid thermal annealing (RTA) process was conducted under 3-different temperatures to analyse the characteristics depending on RTA temperature; 750 ℃, 1000 ℃ and 550 ℃ that was used in additional experiment. A k value of over 30 was obtained in the case of RTA at 750 ℃ and 1000 ℃ by capacitance measurement, which is sufficiently large value. Current-Voltage characteristic showed large leakage current as concerned. However, the current density of the film processed RTA at 750 ℃ was smaller than as-deposited film and that of the film processed RTA at 1000 ℃ increased again. This reversal implies that TiO2 has an optimum RTA temperature at which leakage current is lowest. The RTA process caused development of an interfacial layer that attributes to prevent the leakage current and phase transition of TiO2. TiO2 can have various crystal phase depending on process temperature; amorphous state at the point of deposition, anatase phase below 600 ℃ and rutile phase above 800 ℃. In addition, when TiO2 has anatase phase, it presents larger resistivity than TiO2 with rutile phase. So if the ratio of anatase phase in TiO2 increase, total resistivity of TiO2 also increases. Further study on MIS capacitor using TiO2 processed RTA at 550 ℃ that would have more anatase phase than RTA at 750 ℃ was conducted to confirm that the optimal RTA temperature is in a range lower than 750 ℃. The film annealed at 550 ℃ has lower leakage current than film annealed at 750 ℃. In addition, the crystalline structure of TiO2 annealed at 550 ℃ showed quite similar result to RTA 750 ℃ case, which means the phase of TiO2 changed to anatase. These results provide evidence that the optimal RTA temperature exists under 750 ℃ to minimize leakage current flowing through TiO2.