Statistical Circuit Analysis for Variation-Aware VLSI Design

Abstract

As technology node shrinks, process variation (PV) becomes a major concern in circuit design. Circuit designers consider PVs at various stages of the design because PVs impose uncertainty in circuit performance. In general, the variation-aware design starts with the corner extraction step. After determining the circuit topology and performing initial sizing, the designers extract the corner values of PVs that cause the worst-case circuit performance. The corner extraction is essential because designers can further improve circuit performance when optimizing the design for the corner values. Next, the designers predict the design yield to evaluate the optimization for the corner values. Yield prediction is performed by estimating the distribution of circuit performance. The distribution estimation step helps to determine whether the design meets yield constraints. In this dissertation, statistical circuit analysis algorithms that can be applied to the variation-aware circuit design are proposed. The applications of the proposed algorithms are corner extraction for statistical timing analysis and the estimation of system leakage current distribution. In statistical timing analysis, designers traditionally perform the corner extraction by assuming that all logic gates have their worst-case delay values (e.g. 3 values). However, the probability that all logic gates have worst-case delay values at the same time is too small. Therefore, traditional corner extraction causes too pessimistic results. The pessimistic results of corner extraction make design optimization very difficult, increasing time-to-market. To mitigate the pessimism, a new corner extraction method that uses the relaxed corner values of logic gates in timing analysis is proposed. The proposed method stores the candidates that are less than 3 gate delay and selects one of the candidates as the corner value. A candidate is chosen as the corner value with a certain probability. To determine the probability that the candidate will be selected as the corner value, the proposed method constructs a probability model. The probability model is determined by reflecting the required degree of pessimism reduction of the input circuit. The required degree of pessimism reduction is obtained from the delay information of the K-most critical paths. As a result, the proposed method effectively reduces the pessimism by extracting corner values from candidates (< 3 values), considering the timing information of the input circuit. In experiments, the proposed method extracts the corner values of the logic gates that give system delay yields of 99.87%, 95%, and 85%. The estimation error of the proposed method was less than 2% compared to MC simulation while producing the estimates 5.89 x 104 times faster than MC simulation on average. The next proposed algorithms estimate the system leakage distribution. The designers have difficulty estimating leakage distributions accurately because leakage distributions do not fit well-known functions such as Gaussian and lognormal distributions. Furthermore, the shape of the leakage distribution changes depending on the technology nodes or operating conditions. Therefore, a new approach to utilizing mixture models in estimating leakage distributions is proposed. Gaussian and exponential mixture models are used to represent the leakage distribution. Mixture models can successfully model the changing shapes of leakage distributions regardless of technology nodes or operating conditions because they can cover more various shapes of distributions than a single model. The proposed algorithm provides the number of leakage data required for convergence. In addition, a new method of sequentially adding the leakage distributions represented by the mixture models is proposed. Especially in leakage distribution estimation using exponential mixture models, the accuracy is improved by proposing the elimination of dependencies between leakage data. A proposed component reduction algorithm also improves efficiency. In a goodness-of-fit test on the estimated cumulative density function, the proposed method achieved 43.6 times improvement in accuracy compared to the best results of benchmark methods on average. While achieving improved accuracy, the proposed method takes only a few tens of seconds, which is only 6.43 times larger runtime compared to the fastest benchmark method.