DC Field | Value | Language |
---|---|---|
dc.contributor.author | 이민섭 | - |
dc.date.accessioned | 2022-03-29T03:22:37Z | - |
dc.date.available | 2022-03-29T03:22:37Z | - |
dc.date.issued | 2021 | - |
dc.identifier.other | OAK-2015-08840 | - |
dc.identifier.uri | http://postech.dcollection.net/common/orgView/200000369481 | ko_KR |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/111645 | - |
dc.description | Doctor | - |
dc.description.abstract | This paper presents a synthesized fractional-N digital PLL with a speculative dual-referenced interpolating time-to-digital converter (DI-TDC). The DI-TDC measures a fractional phase by referencing two adjacent quadrant boundaries which are given by a four-phase digitally controlled oscillator. It achieves a robust gain matching to the first order without need of any calibration. By predicting a time region of interest for the next TDC conversion, the power and area overheads for DI-TDC is minimized. Except for DCO and a reference delay chain, the PLL is implemented with register-transfer-level (RTL) behavioral descriptions followed by an automated synthesis. It is fabricated in 28 nm CMOS with an active area of 0.0043 mm2. The PLL shows a wide frequency lock range operating at a supply voltage from 0.3 to 1.2 V, achieving a stable figure-of-merit of better than -220 dB for a supply voltage above 0.6 V. | - |
dc.language | eng | - |
dc.publisher | 포항공과대학교 | - |
dc.title | 0.0043 mm2 0.3-to1.2 V Frequency-Scalable Synthesized Fractional-N Digital PLL with a Speculative Dual-Referenced Interpolating TDC | - |
dc.type | Thesis | - |
dc.contributor.college | 일반대학원 전자전기공학과 | - |
dc.date.degree | 2021- 2 | - |
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