Phase-Difference-Modulation Signaling for Highly-Reflective Interconnects

Abstract

This thesis presents phase-difference-modulation signaling for highly-reflective interconnects. By greatly suppressing reflective intersymbol interferences with two new enabling mechanisms, phase–difference modulation enables cost-efficient high-speed data communication via highly-reflective interfaces. A mathematical analysis is presented, and provides guidelines on how to determine channel and signaling parameters to exploit the two enabling mechanisms based on a newly derived formula of a single bit response of a channel. Based on the mathematical analysis, two transceiver designs using phase-difference modulation are proposed and fabricated in 65-nm CMOS technology. In the first design, phase-difference-modulation without decision feedback equalization is presented for the highly-reflective channels. A phase-difference amplifier is also proposed to relieve the timing constraint of the bit decision at the receiver. By greatly enlarging horizontal eye opening, the phase-difference amplifier greatly reduces the design complexity of the clock recovery circuit. In single-ended mode, the transceiver achieved a maximum speed of 7.8 Gb/s/pin at energy cost of only 1.96 pJ/b while overcoming 10 in-band notches without decision feedback equalization. Also, the phase-difference amplifier enables clock recovery at power and area costs of only 0.12 pJ/b and 550 μm2, respectively, in single-ended 6-Gb/s/pin operation. To extend the applicable channel range, this thesis also proposes the second design that combines phase-difference-modulation signaling with decision feedback equalization technique. By utilizing 2 taps of decision feedback equalization at costs of 1.54x power and 2.49x hardware area than the first design, this second design could achieve the maximum data rate of 7.8 Gb/s/pin through the multi-drop channel with a 2-cm stub whereas the first design without decision feedback equalization is not applicable to this channel.

본 논문에서는 highly-reflective memory interfaces 에서 효율적으로 통신하기 위해 phase-difference modulation (PDM) 을 활용한 송수신기를 제안합니다. PDM 신호 통신에서는 기존 Non-return-to-zero (NRZ) 통신에 비해 reflective ISIs 가 줄어들어 highly reflective memory interfaces 에서 equalization 없이 통신 할 수 있었습니다. 또한 TRX/CDR이 더 신뢰성 있게 동작하기 위해, phase-difference amplifier (PDA) 를 제안하여 RX에서의 빡빡한 timing을 완화하였습니다. PDA 덕분에 PDM 통신에서 수신한 신호를 interpolation함으로써 간단하게 클락 복구를 할 수 있습니다. 그 결과, 구현된 송수신기는 7.8Gb/s/pin, single-ended 동작에서 10개의 notch를 극복하면서 14 tap에 DFE에 해당하는 ISI 억제하였습니다. 또한 6Gbit/s/pin 동작에서 0.12pJ/b의 저전력으로 클락 복구에 성공하였습니다.