Low-Power High-Speed DRAM Interface with Duo-Binary Transmitter and Time- Based Receiver Circuits
- Title
- Low-Power High-Speed DRAM Interface with Duo-Binary Transmitter and Time- Based Receiver Circuits
- Authors
- 채민균
- Date Issued
- 2021
- Publisher
- 포항공과대학교
- Abstract
- A duo-binary signaling has been applied to a transceiver circuit for a low-power high-speed DRAM interface. The transmitter consists of a half-rate voltage-mode time-interleaved mixing duo-binary driver and a 2-tap feed-forward equalizer. The voltage-mode driver is used in this work because it generates more linear output voltage than the current-mode driver for the duo-binary signaling at low supply voltage. A time-based receiver is used for high-speed operation at low supply voltage. A 1-tap look-ahead decision-feedback equalizer scheme is applied to the time-based receiver for the duo-binary decoding operation. The test chip fabricated in a 28 nm low-power CMOS process gives the energy efficiency of 0.41 pJ/b at 12 Gb/s with a 25 cm-long FR-4 micro-strip line and the supply voltage of 0.75V.
- URI
- http://postech.dcollection.net/common/orgView/200000367678
https://oasis.postech.ac.kr/handle/2014.oak/111956
- Article Type
- Thesis
- Files in This Item:
- There are no files associated with this item.
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