삼진 회로의 검증 및 테스팅 방법

Abstract

In recent decades, complementary metal-oxide-semiconductor (CMOS) based binary digital systems have steadily improved in performance. However, the CMOS technology faces fundamental limitations as the feature size decreases. To overcome these limitations, multi-valued logic (MVL) has been suggested. MVL uses more than two logic values, and it can increase the data density. Three-valued (ternary) logic is the first step of MVL, and it is expected that it can reduce the circuit elements and improve the power, performance, and area compared to the binary logic. In this thesis, we propose testing and verification method for the ternary logic circuits. First, ternary to binary converter and binary to ternary converter are proposed, and they enable signal conversion freely between binary and ternary domains. These converters enable communication with existing binary verification interfaces and ternary circuits and enable a mixed circuit in which ternary and binary systems are mixed. Using the converters, ternary logic circuit research can be advanced to a higher level. We also propose a test pattern generation method for the ternary logic circuits. Using this method, we can observe the value discrepancy between the faulty circuit and the correct circuit in the primary output, and detect the stuck-at faults in the ternary logic circuits. This method can ensure the reliability of the manufactured ternary logic circuit and enables ternary logic circuits to be used in many applications.