DC Field | Value | Language |
---|---|---|
dc.contributor.author | 최정원 | - |
dc.date.accessioned | 2022-03-29T03:55:11Z | - |
dc.date.available | 2022-03-29T03:55:11Z | - |
dc.date.issued | 2022 | - |
dc.identifier.other | OAK-2015-09543 | - |
dc.identifier.uri | http://postech.dcollection.net/common/orgView/200000597703 | ko_KR |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/112348 | - |
dc.description | Master | - |
dc.description.abstract | Providing superior error-correcting performance at the algorithm level, the non-binary low-density parity-check (NB-LDPC) code is now expected to be one of the next-generation error correction codes. However, it is hard to implement a high-throughput NB-LDPC decoder in practice due to its impractical processing complexity as well as the excessively long decoding time. Based on the previous extended min-sum (EMS) approach, in this work, we introduce the dual-message EMS decoding algorithm that reduces the processing latency of each iteration by managing multiple messages at a time. The previous two-phase node-level operation is modified to promote the proposed parallel processing without performance degradation, where the delay overheads are minimized by carefully optimizing the internal sorters with input attributes. In addition, the data accessing sequence is precisely modified to reduce the number of waiting cycles, further increasing the overall processing efficiency. Implemented in a 22nm FinFET technology, as a result, the prototype decoder for (160, 80) NB-LDPC codes operates at the speed of 950 MHz, achieving the decoding throughput of more than 7 Gbps, which is 3.2 times faster than the state-of-the-art design. | - |
dc.language | eng | - |
dc.publisher | 포항공과대학교 | - |
dc.title | High-Throughput Non-Binary LDPC Decoder Architecture Using Dual-Message EMS Algorithm | - |
dc.title.alternative | 이중 메시지 확장 최소합 알고리즘을 이용한 초고속 비이진 저밀도 패리티 검사 복호기 아키텍처 | - |
dc.type | Thesis | - |
dc.contributor.college | 일반대학원 전자전기공학과 | - |
dc.date.degree | 2022- 2 | - |
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