A 6Gb/s Transceiver Design with Phase-Difference Modulation Signaling for Multi-drop DRAM Interface

Abstract

In this paper, we designed the phase-difference modulation (PDM) transceiver for the application of PDM signaling in the multi-drop DRAM interface. Because PDM signaling reduced the effect of the reflected signal by positioning the reflected signal between the clock edges, In addition, PDM transceiver did not increase the hardware cost because it does not demand DFE and FFE circuits. With PDM signaling, we implemented the two amplifiers, which make the design complexity of the clock recovery circuit simple: the clock recovery circuit is a simple interpolator. The proposed PDM transceiver was fabricated in 65 nm CMOS technology and verified the performance by simulations. To verify the performance of the PDM signaling, we compared the simulated 6 Gb/s eye diagram in the multi-drop channel with the NRZ signaling. The simulated vertical and horizontal eye sizes in PDM signaling were increased to 60.5 mV and 63.7 ps, respectively; but the simulated eye was closed in NRZ signaling. Therefore, with PDM signaling, the multi-drop memory interfaces with high capacity are feasible without increasing the power and hardware cost.