A Study on Self-Calibration for Low-Noise Digital PLL

Abstract

This work presents a low-noise millimeter-wave fractional-N digital phase-locked-loop (PLL) architecture with a digital-intensive nonlinearity calibration. The proposed architecture combines a Time-AMP (TA) for high detection sensitivity, a Phase-Interpolator (PI) as a coarse digital-to-time-converter (DTC), a fine differential DTC, a time-to-digital-converter (TDC) and a digital block for a self-calibration. The proposed 2-step self-calibration firstly extracts point-by-point calibration codes for every step of PI, and then performs nonlinearity suppression for fine differential DTC. The self-calibration uses only polarity information of TDC output for feedback control. The implemented frequency synthesizer in Verilog corrects error of PI up to 100% and error of fine DTC up to 600%. Also, in the worst case, the integrated jitter is reduced from 146.6fs to 53.03fs.