DRAM 비트라인 센스앰프의 역전압 오프셋보상에 관한 연구

Abstract

The importance of semiconductor tech shrinks is increasing, but the process development becomes more difficult and the development period increases. DRAM cell size is also inevitably decreasing as the DRAM process becomes finer. In the DRAM industry the most important problem is the reduction of this data storage capacity. As the cell size decreases, there is a problem that the offset value required for determining the data of the bit-line sense amplifier (BLSA) continues to decrease. In addition, mismatch between latch translators is increasing due to process miniaturization, making it difficult to operate sense amplifiers. This paper proposes a DRAM offset cancellation amplifier that operates as reverse bias. We designed a latched type sense amplifier suitable for low power without a short current path and using ground voltage as a reference voltage. Our circuit operated from -30 to 90 ℃, and the average power consumption was about 10 nW. Low power characteristics and the reduced area will be useful for high-capacity DRAMs.