A Study on Inner Spacer Formation for Advanced Node Gate-All-Around Field-Effect Transistors

Abstract

Silicon gate-all-around nanosheet (NS) field-effect transistors (NSFETs) are one of the most prominent devices that can replace fin field-effect transistors (FinFETs) in sub-3-nm node, as they can provide improved electrostatics and have high design flexibility compared to FinFETs. In addition, most processes used in FinFETs can be reused in NSFETs, but NSFETs require a precisely controlled inner spacer formation process that has not been used in previous devices. In NSFETs, the gate length of each NS channel and the fringe field between the gate metal and source/drain (S/D) are determined by the inner spacer thickness (TIS). Therefore, TIS should be controlled precisely since the TIS variation (ΔTIS) can degrade DC/AC characteristics significantly. However, the inner spacer formation process requires a SiGe indentation process demanding a high selectivity of SiGe toward Si. In addition, it is vulnerable to etch depth variation in the actual process, so the TIS from the top to the bottom side is not the same. Therefore, the effects of the top, middle, and bottom ΔTIS (ΔTIS,T, ΔTIS,M, and ΔTIS,B, respectively) on the DC/AC performance should be studied separately since impacts of ΔTIS on the performance depend on which inner spacer is varied. It is well known that NSFETs inevitably have S/D recess depth (TSD) variation. In addition, the TSD variation strengthens the leakage path in the punch-through stopper (PTS) region, which adjoins the bottom inner spacer. Since the gate controllability of the parasitic bottom transistor (trpbt) depends on the TIS,B, TSD variation in the PTS region should be considered along with ΔTIS. In this thesis, ΔTIS in sub-3-nm node 3-stacked NSFETs was deeply investigated using TCAD simulation. The sensitivities of DC/AC performance according to each ΔTIS were different, and changed significantly by the TSD variation. Reducing ΔTIS,T and ΔTIS,M is essential to reduce performance variation in the absence of TSD variation, whereas reducing ΔTIS,B is crucial for suppressing the effects of trpbt in NSFETs having TSD variation. Additionally, the ΔTIS,B should be controlled below 1 nm since the TSD variation increases the off-state current sensitivity to ΔTIS,B by a factor of 22.5 in n-type NSFETs. This study compares performance sensitivities to each ΔTIS in an effort and aims to provide insight on the inner spacer development.