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dc.contributor.authorBYUN, YOUNGHOON-
dc.contributor.authorMOON, SEUNGSIK-
dc.contributor.authorPARK, BAESEONG-
dc.contributor.authorKWON, SE JUNG-
dc.contributor.authorLEE, DONGSOO-
dc.contributor.authorPARK, GUNHO-
dc.contributor.authorYOO, EUNJI-
dc.contributor.authorMIN, JUNG GYU-
dc.contributor.authorLEE, YOUNGJOO-
dc.date.accessioned2024-03-06T01:13:06Z-
dc.date.available2024-03-06T01:13:06Z-
dc.date.created2024-02-21-
dc.date.issued2023-06-05-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/121338-
dc.publisherMLSYS-
dc.relation.isPartOf6th Conference on Machine Learning and Systems (MLSys)-
dc.titleSparsity-aware memory interface architecture using stacked XORNet compression for accelerating pruned-DNN models-
dc.typeConference-
dc.type.rimsCONF-
dc.identifier.bibliographicCitation6th Conference on Machine Learning and Systems (MLSys)-
dc.citation.conferenceDate2023-06-04-
dc.citation.conferencePlaceUS-
dc.citation.title6th Conference on Machine Learning and Systems (MLSys)-
dc.contributor.affiliatedAuthorBYUN, YOUNGHOON-
dc.contributor.affiliatedAuthorMOON, SEUNGSIK-
dc.contributor.affiliatedAuthorPARK, GUNHO-
dc.contributor.affiliatedAuthorYOO, EUNJI-
dc.contributor.affiliatedAuthorMIN, JUNG GYU-
dc.contributor.affiliatedAuthorLEE, YOUNGJOO-
dc.description.journalClass1-
dc.description.journalClass1-

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Dept of Electrical Enginrg
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