An Automated Synthesis Framework for Fast Evaluation of Maximum Operating Frequency

Abstract

In this paper, a systematic synthesis framework to quickly identify the maximum operating frequency of very large scale integration (VLSI) circuits is presented. Unlike the manual framework that requires the intervention of a circuit designer to decide the timing constraint to apply, the proposed framework automatically decides the constraint based on a programmable strategy rather than just waiting for the decision by the designer. As a result, the total elapsed times required to find the maximum operating frequency can be greatly shortened.