A Layout Generator of High-Speed Tree-Type Deserializer with Multi-Phase Divider Pohang University of Science and Technology
- Title
- A Layout Generator of High-Speed Tree-Type Deserializer with Multi-Phase Divider Pohang University of Science and Technology
- Authors
- 이재우
- Date Issued
- 2024
- Publisher
- 포항공과대학교
- Abstract
- This paper proposes a suitable structure for the high-speed operation of a dese- rializer and addresses the implementation of layout auto-generation software based on various deserializing ratios. By overcoming the limitations of previous layout au- tomation research, the proposed deserializer structure is optimized for high-speed op- eration, offering superior performance in terms of power consumption and area. Ad- ditionally, the layout generation time is reduced to within seconds, enhancing user flexibility and convenience. This results in a proposed deserializer structure that is low-power and low-area, designed to achieve data speeds of up to 32 Gb/s at a supply voltage of 1V. The implemented layout auto-generation software significantly reduced the time required for manual layout creation, achieving a 47-fold decrease in layout generation time compared to previously researched layout auto-generation software.
- URI
- http://postech.dcollection.net/common/orgView/200000805585
https://oasis.postech.ac.kr/handle/2014.oak/124057
- Article Type
- Thesis
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