Highly efficient 3-stage Doherty power amplifier using gate bias adaption

Abstract

This paper demonstrates a highly efficient 3-stage Doherty power amplifier (PA) employing an envelope tracking (ET) technique. The '3-stage' Doherty PA is the most efficient architecture for a high peak-to-average power ratio (PAPR) signal among the various Doherty PAs. However, because of the lower peaking biases than those of the 'N-way' Doherty PA, the proper load modulation is hard to be achieved. To get proper modulation, the peaking PAs' gate biases have been adaptively controlled using the ET technique, and the peak power and maximum efficiency characteristic along the backed-off output power region is successfully achieved. By ADS and Matlab simulations, the overall behavior of the 3-stage Doherty PA employing the ET technique has been fully analyzed. To maximize the overall efficiency of the proposed 3-stage Doherty PA, the unit PA has been designed using class F-1 PA. For verification, the amplifier is implemented using 5 W and 10 W PEP LDMOSFETs for the 802.16e mobile world interoperability for microwave access (WiMAX) at 1 GHz with a 8.5 dB PAPR. The measured drain efficiency of the proposed 3-stage Doherty PA is 55.5% at an average output power of 37 dBm, which is a 7.54 dB backed-off output power. The digital feedback predistortion (DFBPD) algorithm has been used to linearize the proposed PA considering the ET technique. After linearization, the -33.15 dB of relative constellation error (RCE) performance is achieved, satisfying the system specification. These results show that the 3-stage Doherty employing the ET technique and saturated PA is the most suitable PA for the highly efficient and linear transmitter.