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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Minsoo Choi | - |
| dc.contributor.author | Sim, JY | - |
| dc.contributor.author | Park, HJ | - |
| dc.contributor.author | Kim, B | - |
| dc.date.accessioned | 2016-03-31T08:05:32Z | - |
| dc.date.available | 2016-03-31T08:05:32Z | - |
| dc.date.created | 2014-01-14 | - |
| dc.date.issued | 2013-10 | - |
| dc.identifier.issn | 1598-1657 | - |
| dc.identifier.other | 2013-OAK-0000029811 | - |
| dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/14542 | - |
| dc.description.abstract | This paper explains modeling and analysis of RC-dominant wires for high-speed wireline transceiver design. A closed form formula derived from telegrapher's equation accurately describes a frequency response of an RC-dominant wire, yet it is simple and intuitive for designers to easily understand design trade-offs without a complex numerical equation solver. This paper explains how the model is derived and how it can help designers in example transceiver designs. | - |
| dc.description.statementofresponsibility | X | - |
| dc.language | English | - |
| dc.publisher | IEEK PUBLICATION CENTER | - |
| dc.relation.isPartOf | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
| dc.subject | Channel model | - |
| dc.subject | RC-dominant wires | - |
| dc.subject | wireline transceiver design | - |
| dc.subject | signaling modes | - |
| dc.subject | INTERCONNECTS | - |
| dc.title | A Channel Model of Scaled RC-dominant Wires for High-Speed Wireline Transceiver Design | - |
| dc.type | Article | - |
| dc.contributor.college | 전자전기공학과 | - |
| dc.identifier.doi | 10.5573/JSTS.2013.13.5.482 | - |
| dc.author.google | Choi, M | - |
| dc.author.google | Sim, JY | - |
| dc.author.google | Park, HJ | - |
| dc.author.google | Kim, B | - |
| dc.relation.volume | 13 | - |
| dc.relation.issue | 5 | - |
| dc.relation.startpage | 482 | - |
| dc.relation.lastpage | 491 | - |
| dc.contributor.id | 11082511 | - |
| dc.relation.journal | Journal of Semiconductor Technology and SCience | - |
| dc.relation.index | SCI급, SCOPUS 등재논문 | - |
| dc.relation.sci | SCIE | - |
| dc.collections.name | Journal Papers | - |
| dc.type.rims | ART | - |
| dc.identifier.bibliographicCitation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.13, no.5, pp.482 - 491 | - |
| dc.identifier.wosid | 000327471900009 | - |
| dc.date.tcdate | 2019-01-01 | - |
| dc.citation.endPage | 491 | - |
| dc.citation.number | 5 | - |
| dc.citation.startPage | 482 | - |
| dc.citation.title | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
| dc.citation.volume | 13 | - |
| dc.contributor.affiliatedAuthor | Sim, JY | - |
| dc.contributor.affiliatedAuthor | Park, HJ | - |
| dc.contributor.affiliatedAuthor | Kim, B | - |
| dc.identifier.scopusid | 2-s2.0-84886912790 | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalClass | 1 | - |
| dc.description.wostc | 4 | - |
| dc.description.scptc | 4 | * |
| dc.date.scptcdate | 2018-05-121 | * |
| dc.type.docType | Article | - |
| dc.subject.keywordAuthor | Channel model | - |
| dc.subject.keywordAuthor | RC-dominant wires | - |
| dc.subject.keywordAuthor | wireline transceiver design | - |
| dc.subject.keywordAuthor | signaling modes | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.description.journalRegisteredClass | kci | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalResearchArea | Physics | - |
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- 김병섭KIM, BYUNGSUB
- Dept of Electrical Enginrg