A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs
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- Title
- A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs
- Authors
- Jeon, YJ; Lee, JH; Lee, HC; Jin, KW; Min, KS; Chung, JY; Park, HJ
- Date Issued
- 2004-11
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGI
- Abstract
- The conventional register-controlled delay locked loop (RCDLL) with a single delay line requires a complex logic circuit following the phase comparator to prevent the false lock. A RCDLL with two delay lines was published to reduce the chip area and power consumption by comparing the frequency-divided slow signals. Further reductions of 20% in both chip area and power consumptions were achieved in the RCDLL proposed in this work by using a single delay line. The duty cycle of the clock divider output was adaptively changed between 25% and 50% according to the external clock frequency to minimize the number of delay elements and hence the jitter of DLL output clock. The adaptive-change of duty cycle reduced the peak-to-peak jitter of data output from 800 ps to 400 ps at the data rate of 266 Mb/s in the production 256-Mb DDR SDRAM. The worst-case power consumption and the chip size of the RCDLL chip fabricated by using a 0.15-mum CMOS technology were measured to be 12-mW and 0.16-mm(2), respectively, at the data rate of 400 Mb/s and the supply voltage of 2.5 V.
- Keywords
- LOCKED LOOP; DIGITAL DLL; DRAM
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/17647
- DOI
- 10.1109/JSSC.2004.835809
- ISSN
- 0018-9200
- Article Type
- Article
- Citation
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 39, no. 11, page. 2087 - 2092, 2004-11
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