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Cited 42 time in webofscience Cited 60 time in scopus
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dc.contributor.authorLee, YH-
dc.contributor.authorPark, J-
dc.contributor.authorKim, S-
dc.date.accessioned2016-03-31T13:14:13Z-
dc.date.available2016-03-31T13:14:13Z-
dc.date.created2009-03-20-
dc.date.issued2002-02-
dc.identifier.issn0740-817X-
dc.identifier.other2001-OAK-0000002229-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/19374-
dc.description.abstractIn semiconductor manufacturing, the key production criteria are a short cycle time and the maximization of the production capacity. It is known that the production capacity mainly depends on the bottleneck machines in the photolithography processes used in the fabrication process. In this paper we suggest a model to allow the testing of various policies without losing the main characteristics of the fabrication line. Efficient scheduling rules for the bottlenecks and input rules are also suggested with the objectives of maximizing the production volume under a short cycle time. We have shown that pull type scheduling rules outperform push type rules for most performance measures, and that there exists a good combination of scheduling and input rules. Experimental results also include the relationships among the cycle time, balance rate, production output and delivery performance.-
dc.description.statementofresponsibilityX-
dc.languageEnglish-
dc.publisherKLUWER ACADEMIC PUBL-
dc.relation.isPartOfIIE TRANSACTIONS-
dc.subjectWEIGHTED TARDINESS-
dc.subjectWAFER FABRICATION-
dc.subjectCYCLE TIME-
dc.subjectINDUSTRY-
dc.subjectSYSTEM-
dc.subjectMODELS-
dc.titleExperimental study on input and bottleneck scheduling for a semiconductor fabrication line-
dc.typeArticle-
dc.contributor.college기술경영 대학원 과정-
dc.identifier.doi10.1080/07408170208928860-
dc.author.googleLee, YH-
dc.author.googlePark, J-
dc.author.googleKim, S-
dc.relation.volume34-
dc.relation.issue2-
dc.relation.startpage179-
dc.relation.lastpage190-
dc.contributor.id10073810-
dc.relation.journalIIE TRANSACTIONS-
dc.relation.indexSCI급, SCOPUS 등재논문-
dc.relation.sciSCI-
dc.collections.nameJournal Papers-
dc.type.rimsART-
dc.identifier.bibliographicCitationIIE TRANSACTIONS, v.34, no.2, pp.179 - 190-
dc.identifier.wosid000171291800008-
dc.date.tcdate2019-01-01-
dc.citation.endPage190-
dc.citation.number2-
dc.citation.startPage179-
dc.citation.titleIIE TRANSACTIONS-
dc.citation.volume34-
dc.contributor.affiliatedAuthorKim, S-
dc.identifier.scopusid2-s2.0-0036468738-
dc.description.journalClass1-
dc.description.journalClass1-
dc.description.wostc36-
dc.type.docTypeArticle-
dc.subject.keywordPlusWEIGHTED TARDINESS-
dc.subject.keywordPlusWAFER FABRICATION-
dc.subject.keywordPlusCYCLE TIME-
dc.subject.keywordPlusINDUSTRY-
dc.subject.keywordPlusSYSTEM-
dc.subject.keywordPlusMODELS-
dc.relation.journalWebOfScienceCategoryEngineering, Industrial-
dc.relation.journalWebOfScienceCategoryOperations Research & Management Science-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaOperations Research & Management Science-

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김수영KIM, SOO YOUNG
Div of Humanities and Social Sciences
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