FPGA Implementation of USB 2.0 Full-Speed PHY And Link Chip Using Verilog

Abstract

In this paper, A USB 2.0 full-speed device is implemented in FPGA by using a Verilog synthesis. Full-speed device consists of Physical layer (PHY), Serial Interface Engine (SIE), and Device Specific Logic (DSL). Full-speed PHY works successfully to interface a NAND flash chip to PC. It consists of a clock generator, TX and RX, The TX and RX circuits include a NRZI encoder/decoder, a bit sutffer/unstuffer, and serializer/deserializer. The clock generator accepts a 60MHz clock and generates five 12MHz clock signals which are spaced uniformly in time and synchronized to the 60MHz clock. The five 12MHz clocks are enable signals of TX and RX circuits. The 60MHz clock is used as the clock signal of the TX and RX circuits. The 60MHz clock are used for blind oversampling of CDR. An external 1.5kΩ resistor is connected between the D+ node and VDD to notify the connection of the device PHY to the host PC. Full-speed SIE and DSL are implemented for USB 2.0 full-speed device. It works successfully in a Xilinx Vertex-5 FPGA chip at the data rate of 12Mbps for a mouse application.