DC Field | Value | Language |
---|---|---|
dc.contributor.author | Choi, SW | - |
dc.contributor.author | Lee, HB | - |
dc.contributor.author | Park, HJ | - |
dc.date.accessioned | 2016-04-01T01:59:23Z | - |
dc.date.available | 2016-04-01T01:59:23Z | - |
dc.date.created | 2009-02-28 | - |
dc.date.issued | 2006-03 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.other | 2006-OAK-0000005743 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/24161 | - |
dc.description.abstract | A current-mode differential signaling of three data over two pairs of transmission lines increases the effective maximum data rate per pair of transmission lines by about 37% over the conventional pure differential signaling. Each of two data is transmitted as a half-swing differential signal over a pair of transmission lines. The third data is transmitted as a half-swing complementary common-mode signal of the two pairs of transmission lines. Both a single-tap pre-emphasis and a single-tap decision feedback equalizer are combined with this work. Adding a D flip-flop between the equalizer amplifier and the MUX embedded D flip-flop of receiver enables 4-Gb/s operation of receiver. The chip fabricated by using a 0.25-mu m CMOS process shows the maximum data rates of 4 and 3.2 Gb/s over 20- and 60-cm-long FR4 transmission lines, respectively, with bit-error rate below 1E-12. | - |
dc.description.statementofresponsibility | X | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGI | - |
dc.relation.isPartOf | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.subject | complementary common-mode | - |
dc.subject | current-mode | - |
dc.subject | differential signaling | - |
dc.subject | look-ahead decision feedback equalization (DFE) | - |
dc.subject | MUX embedded D flip-flop | - |
dc.subject | pre-emphasis | - |
dc.subject | three data over four conductors | - |
dc.subject | TRANSMITTER | - |
dc.title | A three-data differential signaling over four conductors with pre-emphasis and equalization: A CMOS current mode implementation | - |
dc.type | Article | - |
dc.contributor.college | 전자전기공학과 | - |
dc.identifier.doi | 10.1109/JSSC.2005.864117 | - |
dc.author.google | Choi, SW | - |
dc.author.google | Lee, HB | - |
dc.author.google | Park, HJ | - |
dc.relation.volume | 41 | - |
dc.relation.issue | 3 | - |
dc.relation.startpage | 633 | - |
dc.relation.lastpage | 641 | - |
dc.contributor.id | 10071836 | - |
dc.relation.journal | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.relation.index | SCI급, SCOPUS 등재논문 | - |
dc.relation.sci | SCI | - |
dc.collections.name | Journal Papers | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.41, no.3, pp.633 - 641 | - |
dc.identifier.wosid | 000235764000011 | - |
dc.date.tcdate | 2019-01-01 | - |
dc.citation.endPage | 641 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 633 | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 41 | - |
dc.contributor.affiliatedAuthor | Park, HJ | - |
dc.identifier.scopusid | 2-s2.0-33644655649 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 10 | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | complementary common-mode | - |
dc.subject.keywordAuthor | current-mode | - |
dc.subject.keywordAuthor | differential signaling | - |
dc.subject.keywordAuthor | look-ahead decision feedback equalization (DFE) | - |
dc.subject.keywordAuthor | MUX embedded D flip-flop | - |
dc.subject.keywordAuthor | pre-emphasis | - |
dc.subject.keywordAuthor | three data over four conductors | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
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