Fingerprinting: Bounding Soft-Error-Detection Latency and Bandwidth
SCIE
SCOPUS
- Title
- Fingerprinting: Bounding Soft-Error-Detection Latency and Bandwidth
- Authors
- Smolens, JC; Gold, BT; Kim, J; Falsafi, B; Hoe, JC; Nowatzyk, AG
- Date Issued
- 2004-11
- Publisher
- ACM
- Abstract
- Recent studies have suggested that the soft-error rate in microprocessor logic will become a reliability concern by 2010. This paper proposes an efficient error detection technique, called fingerprinting, that detects differences in execution across a dual modular redundant (DMR) processor pair. Fingerprinting summarizes a processor's execution history in a hash-based signature; differences between two mirrored processors are exposed by comparing their fingerprints. Fingerprinting tightly bounds detection latency and greatly reduces the interprocessor communication bandwidth required for checking. This paper presents a study that evaluates fingerprinting against a range of current approaches to error detection. The result of this study shows that fingerprinting is the only error detection mechanism that simultaneously allows high-error coverage, low error detection bandwidth, and high I/O performance.
- Keywords
- Soft errors; error detection; dual modular redundancy (DMR); backwards error recovery (BER)
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/25107
- DOI
- 10.1145/1037187.1024420
- ISSN
- 0362-1340
- Article Type
- Article
- Citation
- ACM SIGPLAN NOTICES, vol. 39, no. 11, page. 224 - 234, 2004-11
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