DC Field | Value | Language |
---|---|---|
dc.contributor.author | Youngsok Kim | - |
dc.contributor.author | Jaewon Lee | - |
dc.contributor.author | Donggyu Kim | - |
dc.contributor.author | Kim, J | - |
dc.date.accessioned | 2016-04-01T08:09:53Z | - |
dc.date.available | 2016-04-01T08:09:53Z | - |
dc.date.created | 2014-02-04 | - |
dc.date.issued | 2014-07 | - |
dc.identifier.issn | 1556-6056 | - |
dc.identifier.other | 2014-OAK-0000028701 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/27368 | - |
dc.description.abstract | Programmer-managed GPU memory is a major challenge in writing GPU applications. Programmers must rewrite and optimize an existing code for a different GPU memory size for both portability and performance. Alternatively, they can achieve only portability by disabling GPU memory at the cost of significant performance degradation. In this paper, we propose ScaleGPU, a novel GPU architecture to enable high-performance memory-unaware GPU programming. ScaleGPU uses GPU memory as a cache of CPU memory to provide programmers a view of CPU memory-sized programming space. ScaleGPU also achieves high performance by minimizing the amount of CPU-GPU data transfers and by utilizing the GPU memory's high bandwidth. Our experiments show that ScaleGPU can run a GPU application on any GPU memory size and also improves performance significantly. For example, ScaleGPU improves the performance of the hotspot application by similar to 48% using the same size of GPU memory and reduces its memory size requirement by similar to 75% maintaining the target performance. | - |
dc.description.statementofresponsibility | X | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.relation.isPartOf | IEEE COMPUTER ARCHITECTURE LETTERS | - |
dc.title | ScaleGPU: GPU Architecture for Memory-Unaware GPU Programming | - |
dc.type | Article | - |
dc.contributor.college | 컴퓨터공학과 | - |
dc.identifier.doi | 10.1109/L-CA.2013.19 | - |
dc.author.google | Kim, Y | - |
dc.author.google | Lee, J | - |
dc.author.google | Kim, D | - |
dc.author.google | Kim, J | - |
dc.relation.volume | 13 | - |
dc.relation.issue | 2 | - |
dc.relation.startpage | 101 | - |
dc.relation.lastpage | 104 | - |
dc.contributor.id | 10694089 | - |
dc.relation.journal | IEEE COMPUTER ARCHITECTURE LETTERS | - |
dc.relation.sci | SCI | - |
dc.collections.name | Journal Papers | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE COMPUTER ARCHITECTURE LETTERS, v.13, no.2, pp.101 - 104 | - |
dc.identifier.wosid | 000346979300012 | - |
dc.date.tcdate | 2019-02-01 | - |
dc.citation.endPage | 104 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 101 | - |
dc.citation.title | IEEE COMPUTER ARCHITECTURE LETTERS | - |
dc.citation.volume | 13 | - |
dc.contributor.affiliatedAuthor | Kim, J | - |
dc.identifier.scopusid | 2-s2.0-84937544717 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 5 | - |
dc.description.scptc | 4 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.type.docType | Article | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
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