Electrostatic Discharge Robustness of Si Nanowire Field-Effect Transistors
- Title
- Electrostatic Discharge Robustness of Si Nanowire Field-Effect Transistors
- Authors
- Liu, W; Liou, JJ; Chung, A; Jeong, YH; Chen, WC; Lin, HC; null
- Date Issued
- 2009-09
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Abstract
- Electrostatic discharge (ESD) performance of N-type double-gated Si nanowire (NW) thin-film transistors is investigated, for the first time, using the transmission line pulsing technique. The ESD robustness of these devices depends on the NW dimension, number of channels, plasma treatment, and layout topology. The failure currents, leakage currents, and ON-state resistances are characterized, and possible ESD protection applications of these devices for future NW field-effect-transistor-based integrated circuits are also discussed.
- Keywords
- Electrostatic discharge (ESD); failure current I(t2); nanowire (NW) field-effect transistor; ON-state resistance; DEVICES
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/27855
- DOI
- 10.1109/LED.2009.2025610
- ISSN
- 0741-3106
- Article Type
- Article
- Files in This Item:
- There are no files associated with this item.
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