Design of an Efficient Charge-Trapping Layer with a Built-In Tunnel Barrier for Reliable Organic-Transistor Memory
SCIE
SCOPUS
- Title
- Design of an Efficient Charge-Trapping Layer with a Built-In Tunnel Barrier for Reliable Organic-Transistor Memory
- Authors
- Park, YS; Lee, JS
- Date Issued
- 2015-01-27
- Publisher
- ADVANCED MATERIALS
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/35869
- DOI
- 10.1002/ADMA.201404625
- ISSN
- 0935-9648
- Article Type
- Article
- Citation
- ADVANCED MATERIALS, vol. 27, no. 4, page. 706 - 711, 2015-01-27
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- There are no files associated with this item.
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