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Cited 2 time in webofscience Cited 2 time in scopus
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dc.contributor.authorJee, D.-W-
dc.contributor.authorPark, S.-J-
dc.contributor.authorPark, H.-J-
dc.contributor.authorSim, J.-Y.-
dc.date.accessioned2017-07-19T12:28:24Z-
dc.date.available2017-07-19T12:28:24Z-
dc.date.created2011-04-18-
dc.date.issued2008-01-
dc.identifier.issn0886-5930-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/35872-
dc.description.abstractThis paper presents a new architecture of digitally controlled algorithmic OP amp suitable for scaled CMOS technologies. With inverter-based gain stages and digitally-assisted damping control, the amplifier achieves high-gain and wide input/output ranges even at the minimally allowable supply voltage by digital circuits. The amplifier, implemented in a standard 0.18 mu m CMOS, shows a DC gain of 73 dB and 95 % settling time of 41 ns at 0.5 V step input.-
dc.languageEnglish-
dc.publisher.-
dc.relation.isPartOfProceedings of the Custom Integrated Circuits Conference-
dc.titleA low-voltage OP amp with digitally controlled algorithmic approximation-
dc.typeArticle-
dc.identifier.doi10.1109/CICC.2008.4672131-
dc.type.rimsART-
dc.identifier.bibliographicCitationProceedings of the Custom Integrated Circuits Conference, pp.499 - 502-
dc.identifier.wosid000262643900109-
dc.date.tcdate2019-03-01-
dc.citation.endPage502-
dc.citation.startPage499-
dc.citation.titleProceedings of the Custom Integrated Circuits Conference-
dc.contributor.affiliatedAuthorPark, H.-J-
dc.identifier.scopusid2-s2.0-57849146114-
dc.description.journalClass1-
dc.description.journalClass1-
dc.description.wostc2-
dc.description.scptc2*
dc.date.scptcdate2018-05-121*
dc.type.docTypeProceedings Paper-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-

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박홍준PARK, HONG JUNE
Dept of Electrical Enginrg
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