DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jae Hoon Kim | - |
dc.contributor.author | Wook Kim | - |
dc.contributor.author | Kim, YH | - |
dc.date.accessioned | 2017-07-19T12:39:05Z | - |
dc.date.available | 2017-07-19T12:39:05Z | - |
dc.date.created | 2016-03-07 | - |
dc.date.issued | 2015-11 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/36196 | - |
dc.description.abstract | This brief presents an efficient approach to statistical static timing analysis (STA), which estimates the system delay of statistical STA through deterministic STA. In statistical STA, the system delay is modeled as a function of random variables, so it is commonly expressed as a probability density function (pdf). Therefore, to estimate the system delay of statistical STA through deterministic STA, we must find the relationship between an arbitrary percentile point on the pdf of the system delay and the gate delays used in deterministic STA. However, there is no closed-form equation for an arbitrary percentile point on the pdf of the system delay, we derive an analytic expression for the upper bound of an arbitrary percentile point on the pdf of the system delay. This allows us to obtain the corresponding gate delays that are used to estimate the upper bound of the percentile point on the pdf of the system delay through deterministic STA. Experimental results indicate that the percentile point on the pdf of the system delay obtained with statistical STA is strictly bounded by the upper bound of the percentile point obtained with the proposed method within an average 6% difference range. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.title | Efficient Statistical Timing Analysis Using Deterministic Cell Delay Models | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/TVLSI.2014.2364736 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.23, no.11, pp.2709 - 2713 | - |
dc.identifier.wosid | 000364209000036 | - |
dc.date.tcdate | 2019-02-01 | - |
dc.citation.endPage | 2713 | - |
dc.citation.number | 11 | - |
dc.citation.startPage | 2709 | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 23 | - |
dc.contributor.affiliatedAuthor | Kim, YH | - |
dc.identifier.scopusid | 2-s2.0-84909983138 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 3 | - |
dc.description.scptc | 2 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.type.docType | Article | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
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