Structural reliability evaluation of low-k nanoporous dielectric interlayers integrated into microelectronic devices

Abstract

As integrated microelectronic circuit device dimensions continue to shrink, low dielectric constant (low-k) interlayer dielectrics are required for minimizing RC signal delay, capacitive coupling noise, and power consumption. The implementation of low-k materials in an interconnected structure, however, is known to be a very difficult task because of many criteria imposed by the structural functionality and the integration process. Here, we report structural reliability evaluation for the integration of low-k nanoporous organosillicate dielectrics into a multilayer structure, involving capping, chemical mechanical polishing (CMP), post-CMP cleaning, and thermal annealing processes. We have successfully investigated the structural reliability of the low-k dielectric layer subjected to such harsh processes using synchrotron grazing incidence X-ray scattering and reflectivity (GIXS and XR) analyses. This study additionally demonstrated that synchrotron GIXS and XR techniques are very powerful tools for providing valuable, accurate insight into the nanopore structure in low-k dielectric thin layers and the structural changes with the integration process conditions.