DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Y | - |
dc.contributor.author | Jung, J | - |
dc.contributor.author | Park, IC | - |
dc.date.accessioned | 2017-07-19T13:45:23Z | - |
dc.date.available | 2017-07-19T13:45:23Z | - |
dc.date.created | 2017-02-22 | - |
dc.date.issued | 2016-02 | - |
dc.identifier.issn | 1745-1353 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/37528 | - |
dc.description.abstract | This paper presents a novel low-power decoder architecture for the (36420, 32778) binary LDPC code targeting energy-efficient NAND-flash-based mobile devices. The proposed energy-scalable decoding algorithm reduces the operating bit-width of decoding function units at the early-use stage where the channel condition is good enough to lower the precision of computation. Based on a flexible adder structure, the decoding energy of the proposed LDPC decoder can be reduced by freezing the unnecessary parts of hardware resources. A prototype 4KB LDPC decoder is designed in a 65nm CMOS technology, which achieves an average decoding throughput of 8.13Gb/s with 1.2M equivalent gates. The power consumption of the decoder ranges from 397mW to 563mW depending on operating conditions. | - |
dc.language | English | - |
dc.publisher | IEICE | - |
dc.relation.isPartOf | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.title | Energy-scalable 4KB LDPC decoding architecture for NAND-flash-based storage systems | - |
dc.type | Article | - |
dc.identifier.doi | 10.1587/TRANSELE.E99.C.293 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEICE TRANSACTIONS ON ELECTRONICS, v.E99C, no.2, pp.291 - 301 | - |
dc.identifier.wosid | 000381557500019 | - |
dc.date.tcdate | 2019-02-01 | - |
dc.citation.endPage | 301 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 291 | - |
dc.citation.title | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.citation.volume | E99C | - |
dc.contributor.affiliatedAuthor | Lee, Y | - |
dc.identifier.scopusid | 2-s2.0-84957649592 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 3 | - |
dc.description.scptc | 4 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.type.docType | Article | - |
dc.subject.keywordPlus | DECISION ERROR-CORRECTION | - |
dc.subject.keywordPlus | RECOVERY SCHEMES | - |
dc.subject.keywordPlus | MEMORY | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | PERFORMANCE | - |
dc.subject.keywordPlus | CODES | - |
dc.subject.keywordAuthor | energy-efficient design | - |
dc.subject.keywordAuthor | forward error-correction | - |
dc.subject.keywordAuthor | NAND flash memory | - |
dc.subject.keywordAuthor | VLSI designs | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
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