DC Field | Value | Language |
---|---|---|
dc.contributor.author | Woo, J | - |
dc.contributor.author | Belmonte, A | - |
dc.contributor.author | Redolfi, A | - |
dc.contributor.author | Hwang, H | - |
dc.contributor.author | Jurczak, M | - |
dc.contributor.author | Goux, L | - |
dc.date.accessioned | 2017-07-19T13:50:22Z | - |
dc.date.available | 2017-07-19T13:50:22Z | - |
dc.date.created | 2017-02-27 | - |
dc.date.issued | 2016-05 | - |
dc.identifier.issn | 2168-6734 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/37704 | - |
dc.description.abstract | In this paper, we optimize a WO3\Al2O3 bilayer serving as the electrolyte of a conductive bridge RAM device using a Cu-based supply layer. By introducing a WO3 layer formed by thermal oxidation of a W plug, the hourglass shape of the conductive filament is desirably controlled, enabling excellent switching behavior. We demonstrate a clear improvement of the microstructure and density of the WO3 layer by increasing the oxidation time and temperature, resulting in a strong increase of the high-resistance-state breakdown voltage. The high quality WO3 microstructure allows thus the use of a larger reset pulse amplitude resulting both in larger memory window and failure-free write cycling. | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.relation.isPartOf | IEEE Journal of the Electron Devices Society | - |
dc.title | Introduction of WO3 Layer in a Cu-Based Al2O3 Conductive Bridge RAM System for Robust Cycling and Large Memory Window | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/JEDS.2016.2526632 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE Journal of the Electron Devices Society, v.4, no.3, pp.163 - 166 | - |
dc.identifier.wosid | 000374869400009 | - |
dc.date.tcdate | 2019-02-01 | - |
dc.citation.endPage | 166 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 163 | - |
dc.citation.title | IEEE Journal of the Electron Devices Society | - |
dc.citation.volume | 4 | - |
dc.contributor.affiliatedAuthor | Hwang, H | - |
dc.identifier.scopusid | 2-s2.0-84964894597 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 9 | - |
dc.description.scptc | 7 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.description.isOpenAccess | Y | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Conductive-bridge RAM (CBRAM) | - |
dc.subject.keywordAuthor | endurance | - |
dc.subject.keywordAuthor | low current operation | - |
dc.subject.keywordAuthor | memory window | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
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