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An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications SCIE SCOPUS

Title
An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications
Authors
Choi, SeungnamKu, Hwan-SeokSon, HyunwooKIM, BYUNGSUBPARK, HONG JUNESIM, JAE YOON
Date Issued
2018-02
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Abstract
This paper presents an asynchronous-clocking successive approximation register (SAR) analog-to-digital converter (ADC) suitable for ultralow-power fine-precision sensor applications whose signal bandwidth is in the kilohertz range. The performance-limiting issues of comparator noise and capacitor mismatch in SAR ADC are resolved by a residue integration scheme combined with a dynamic element matching (DEM), achieving a high resolution without imposing extra burden on the design of residue amplifier and comparator. The prototype 16-bit 2 kS/s SAR ADC is fabricated using 180-nm CMOS process in an area of 0.68 mm2. Measurements show 84.6-dB signal to noise and distortion ratio and 98.2-dB spurious-free dynamic range at the Nyquist input frequency. The ADC dissipates 7.93 μW from supply voltage of 1.8 V and achieves a Schreier figure of merit of 165.6 dB.
Keywords
Approximation theory; Comparator circuits; Comparators (optical); Frequency converters; Signal to noise ratio; Surveying; Analog to digital converters; Dynamic element matching; Low power sensor; Nyquist rate; Successive approximation register; Analog to digital conversion
URI
https://oasis.postech.ac.kr/handle/2014.oak/41349
DOI
10.1109/JSSC.2017.2774287
ISSN
0018-9200
Article Type
Article
Citation
IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 53, no. 2, page. 404 - 417, 2018-02
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김병섭KIM, BYUNGSUB
Dept of Electrical Enginrg
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