DC Field | Value | Language |
---|---|---|
dc.contributor.author | CHATTERJEE, NILADRISH | - |
dc.contributor.author | O'CONNOR, MIKE | - |
dc.contributor.author | LEE, DONGHYUK | - |
dc.contributor.author | JOHNSON, DANIEL | - |
dc.contributor.author | KECKLER, STEPHEN | - |
dc.contributor.author | RHU, MINSOO | - |
dc.contributor.author | DALLY, WILLIAM | - |
dc.date.accessioned | 2018-05-11T02:53:47Z | - |
dc.date.available | 2018-05-11T02:53:47Z | - |
dc.date.created | 2018-03-29 | - |
dc.date.issued | 2017-02-08 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/43252 | - |
dc.description.abstract | This paper proposes an energy-efficient, high-throughput DRAM architecture for GPUs and throughput processors. In these systems, requests from thousands of concurrent threads compete for a limited number of DRAM row buffers. As a result, only a fraction of the data fetched into a row buffer is used, leading to significant energy overheads. Our proposed DRAM architecture exploits the hierarchical organization of a DRAM bank to reduce the minimum row activation granularity. To avoid significant incremental area with this approach, we must partition the DRAM datapath into a number of semi-independent subchannels. These narrow subchannels increase data toggling energy which we mitigate using a static data reordering scheme designed to lower the toggle rate. This design has 35% lower energy consumption than a die-stacked DRAM with 2.6% area overhead. The resulting architecture, when augmented with an improved memory access protocol, can support parallel operations across the semi-independent subchannels, thereby improving system performance by 13% on average for a range of workloads. | - |
dc.publisher | IEEE | - |
dc.relation.isPartOf | IEEE International Symposium on High Performance Computer Architecture | - |
dc.relation.isPartOf | Proceedings of the 23rd IEEE International Symposium on High Performance Computer Architecture | - |
dc.title | Architecting an Energy-Efficient DRAM System for GPUs | - |
dc.type | Conference | - |
dc.type.rims | CONF | - |
dc.identifier.bibliographicCitation | IEEE International Symposium on High Performance Computer Architecture , pp.73 - 84 | - |
dc.citation.conferenceDate | 2017-02-04 | - |
dc.citation.conferencePlace | US | - |
dc.citation.endPage | 84 | - |
dc.citation.startPage | 73 | - |
dc.citation.title | IEEE International Symposium on High Performance Computer Architecture | - |
dc.contributor.affiliatedAuthor | RHU, MINSOO | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
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