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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 조화숙 | - |
| dc.contributor.author | 성기환 | - |
| dc.contributor.author | 김병섭 | - |
| dc.contributor.author | 박홍준 | - |
| dc.contributor.author | 심재윤 | - |
| dc.date.accessioned | 2018-05-24T01:52:15Z | - |
| dc.date.available | 2018-05-24T01:52:15Z | - |
| dc.date.created | 2017-08-23 | - |
| dc.date.issued | 2017-02-05 | - |
| dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/47989 | - |
| dc.publisher | IEEE | - |
| dc.relation.isPartOf | IEEE International Solid-State Circuits Conference | - |
| dc.relation.isPartOf | IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE | - |
| dc.title | A 0.0047mm2 Highly Synthesizable TDC- and DCO-Less Fractional-N PLL with a Seamless Lock Range of fREF to 1GHz | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.identifier.bibliographicCitation | IEEE International Solid-State Circuits Conference | - |
| dc.citation.conferencePlace | US | - |
| dc.citation.title | IEEE International Solid-State Circuits Conference | - |
| dc.contributor.affiliatedAuthor | 조화숙 | - |
| dc.contributor.affiliatedAuthor | 성기환 | - |
| dc.contributor.affiliatedAuthor | 김병섭 | - |
| dc.contributor.affiliatedAuthor | 박홍준 | - |
| dc.contributor.affiliatedAuthor | 심재윤 | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalClass | 1 | - |
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Related Researcher
- 김병섭KIM, BYUNGSUB
- Dept of Electrical Enginrg