DC Field | Value | Language |
---|---|---|
dc.contributor.author | Youn, Yelim | - |
dc.contributor.author | Kim, Kwangmin | - |
dc.contributor.author | Sim, Jae-Yoon | - |
dc.contributor.author | Park, Hong-June | - |
dc.contributor.author | Kim, Byungsub | - |
dc.date.accessioned | 2018-06-15T05:22:28Z | - |
dc.date.available | 2018-06-15T05:22:28Z | - |
dc.date.created | 2017-09-14 | - |
dc.date.issued | 2017-09 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/50410 | - |
dc.description.abstract | This paper disproves the worst read scenario of a ReRAM crossbar array. If the previously believed worst read scenario is not the worst one, the read margin evaluated based on the scenario can be incorrect. We explored for read scenario worse than the previously believed worst scenario by wisely sampling scenarios and iteratively searching for the worse one. In experiment, our algorithm successfully found the scenario worse than the previously believed one, disproving the previously believed worst read scenario. Our results show that the sensing window estimated by the incorrect previously believed worst scenario is 14 times as large as the estimation by the worst scenario found by our algorithm. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.subject | DEVICE CHARACTERISTICS | - |
dc.subject | RRAM | - |
dc.subject | MEMORIES | - |
dc.title | Investigation on the Worst Read Scenario of a ReRAM Crossbar Array | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/TVLSI.2017.2710140 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.9, pp.2402 - 2410 | - |
dc.identifier.wosid | 000408425400003 | - |
dc.date.tcdate | 2019-02-01 | - |
dc.citation.endPage | 2410 | - |
dc.citation.number | 9 | - |
dc.citation.startPage | 2402 | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 25 | - |
dc.contributor.affiliatedAuthor | Kim, Kwangmin | - |
dc.contributor.affiliatedAuthor | Sim, Jae-Yoon | - |
dc.contributor.affiliatedAuthor | Park, Hong-June | - |
dc.contributor.affiliatedAuthor | Kim, Byungsub | - |
dc.identifier.scopusid | 2-s2.0-85021969154 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 1 | - |
dc.type.docType | Article | - |
dc.subject.keywordPlus | DEVICE CHARACTERISTICS | - |
dc.subject.keywordPlus | RRAM | - |
dc.subject.keywordPlus | MEMORIES | - |
dc.subject.keywordAuthor | Crossbar array | - |
dc.subject.keywordAuthor | read margin | - |
dc.subject.keywordAuthor | resistive random access memory (ReRAM) | - |
dc.subject.keywordAuthor | search algorithm | - |
dc.subject.keywordAuthor | orst read operation scenario | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
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