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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 김영환 | - |
| dc.contributor.author | Kai Chen | - |
| dc.date.accessioned | 2018-06-19T03:52:25Z | - |
| dc.date.available | 2018-06-19T03:52:25Z | - |
| dc.date.created | 2016-02-29 | - |
| dc.date.issued | 2015-04-28 | - |
| dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/71470 | - |
| dc.publisher | IEEE Circuits and Systems Society | - |
| dc.relation.isPartOf | VLSI Design, Automation and Test (VLSI-DAT 2015) | - |
| dc.relation.isPartOf | VLSI DESIGN, AUTOMATION AND TEST | - |
| dc.title | Current Source Model of Combinational Logic Gates for Accurate Gate-level Circuit Analysis and Timing Analysis | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.identifier.bibliographicCitation | VLSI Design, Automation and Test (VLSI-DAT 2015) | - |
| dc.citation.conferenceDate | 2015-04-27 | - |
| dc.citation.conferencePlace | CH | - |
| dc.citation.title | VLSI Design, Automation and Test (VLSI-DAT 2015) | - |
| dc.contributor.affiliatedAuthor | 김영환 | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalClass | 1 | - |
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- 김영환KIM, YOUNG HWAN
- Dept of Electrical Enginrg