Thesis
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 양형균 | en_US |
| dc.date.accessioned | 2015-02-25T14:02:10Z | - |
| dc.date.available | 2015-02-25T14:02:10Z | - |
| dc.date.issued | 2009 | en_US |
| dc.identifier.other | OAK-2015-06652 | en_US |
| dc.identifier.uri | http://postech.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000001909790 | en_US |
| dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/9033 | - |
| dc.description | Master | en_US |
| dc.language | kor | en_US |
| dc.publisher | 포항공과대학교 | en_US |
| dc.rights | BY_NC_ND | en_US |
| dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/2.0/kr | en_US |
| dc.title | 다양한 VLSI 설계 단계에서의 확률 통계적인 Timing 해석의 유효성 | en_US |
| dc.title.alternative | Effentiveness of Statistical Static Timing Analysis at Various VLSI Design Levels | en_US |
| dc.type | Thesis | en_US |
| dc.contributor.college | 일반대학원 전자전기공학과 | en_US |
| dc.date.degree | 2009-08 | en_US |
| dc.type.docType | Thesis | - |
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