Statistical Timing Analysis Using Deterministic Cell Delay Models for VLSI Designs

Abstract

Aggressive technology scaling in feature size has propelled designers to integrate millions of transistors on a single die. However, technology scaling increases process variability, thus resulting in fluctuations in device properties and undesirable circuit performance variations. Because a large performance variation may induce yield loss, an analysis method that considers variation in circuit performance is required in modern VLSI design. Two conventional methods that consider variation in circuit performance are worst-case analysis and Monte Carlo simulation based analysis. However, worst-case analysis and Monte Carlo simulation based analysis cannot be employed in advanced technology because of accuracy and complexity problems, respectively. Therefore, statistical timing analysis emerged as a promising method for analyzing the complex effect of process variations on system timing. In statistical timing analysis, the delay and arrival time in a system are modeled with random variables (RVs), and the cumulative distribution function (CDF) of arrival time is typically used to evaluate system timing. Unlike deterministic timing analysis methods that generate a pass/fail outcome (whether a VLSI design satisfies the given timing specification or not), statistical timing analysis analytically evaluates the probability of a design to meet a given timing specification. Specifically, statistical timing analyses do not predict worst-case timing but parametric yield. Therefore, statistical timing analysis is more accurate than the traditional worst-case analysis and more efficient than Monte Carlo simulation based analysis. Despite its advantages, statistical timing analysis cannot be easily employed in modern circuit design process because though the system delay at gate level can be estimated, statistical timing analysis is slower than worst-case analysis for systems with billions of logic gates. Moreover, conventional deterministic design flow to statistical analysis flow conversion requires too many design process modifications. This dissertation presents an efficient statistical timing analysis method that considers variation in circuit performance. The proposed method is based on deterministic timing analysis method; however, the results of statistical timing analysis can be estimated. To estimate the results of statistical timing analysis using the deterministic timing analysis method, the statistical system delay is modeled as an arbitrary z-sigma value on arrival time distribution, and the deterministic system delay is then modeled. The deterministic gate delays are then determined on the basis of z. Finally, deterministic timing analysis is performed using the calculated gate delays to produce z-sigma value on the arrival time distribution. However, a closed-form equation does not exist for the z-sigma value on the arrival time distribution; therefore, an analytic expression is derived for the upper bound of the z-sigma value on the arrival time distribution by analyzing the characteristics of the statistical MAX operation, which is a key function in statistical timing analysis. The corresponding gate delays can then be obtained and used to analytically estimate the upper bound of an arbitrary value on the arrival time distribution. A major contribution of the proposed method is that the statistical timing analysis results can be estimated through deterministic timing analysis within an acceptable difference range. Because the proposed method uses the deterministic timing analysis method for estimating the statistical timing analysis results, it can only resolve the compatibility problems of existing statistical timing analysis methods. The proposed method can be used to effectively explore design space in advanced technology comprising billions of logic gates in a system. In the experiments with an industrial 32-nm technology model and ISCAS 85 and 89 benchmark circuits, the results of the proposed method vary from those of statistical timing analysis by less than 8% in all the cases. Further, the proposed method is much faster than statistical timing analysis. In the case of the s35932 circuit having 6300 gates, the proposed method is 45.45 times faster than statistical timing analysis. Because the runtime difference between the proposed and statistical timing analysis methods increases as the number of gates in a system increase, the proposed method can be effectively used for advanced technology comprising billions of logic gates in a system. In conclusion, the proposed statistical timing analysis method is effective for exploring design space in advanced technology and maintains the analysis accuracy of the statistical timing analysis method.