A Study on Source and Drain Series Resistance of Gate-All-Around Si-Nanowire FETs

Abstract

The source/drain (S/D) series resistance (Rsd) in scaled gate-all-around nanowire field-effect transistors (GAA NWFETs) is investigated. The portion of Rsd in total resistance become large as devices is scaled. Especially, the control of doping profile in nanowire channel is difficult due to very small volume of nanowire and this cause higher parasitic Rsd. Also, NWFETs possess a complicated junction structure that is changed from one dimension in the channel to three dimension in S/D pad which induce complex components in the Rsd such as spreading, extension, sheet, deep S/D, and contact resistance. Therefore, the exact extraction of Rsd is important. Conventional methods to extract the Rsd such as CRM, YΦ method, and Y-function technique are summarized and applicability of these methods to NWFETs is investigated. These methods are turned out to be unsuitable for the Rsd extraction of the NWFETs. The NWFETs with the channel diameter (dNW) from 7 to 12 nm and physical channel length (Leff) from 14 to 134 nm with a thickness of 3.4 nm SiO2 oxide layer surrounding <110>-oriented silicon nanowire channel is investigated. The Rsd extraction method lately proposed is modified for NWFETs because the NWFETs have fluctuating characteristics in Id and physical understanding of the NWFETs is insufficient. The modified Rsd extraction method that uses an optimized Id equation and a threshold voltage (Vth) extraction procedure for NWFETs is proposed. The Id equation is modified for the geometry of the NWFET, and the Vth is obtained from the linear Y-function that can be observed in NWFETs because of volume inversion. A inevitable assumption for this procedure is experimentally confirmed using the Y-function, and equations fit the measured data perform well; this confirm the validity of the modified Id equations for the NWFETs. The Rsd is perfectly extracted in all NWFETs and it is observed to be dependent on the dNW when normalized by dNW, indicating that the extension resistance is the dominant component in the total Rsd. The Rsd normalized by channel diameter dNW in p-type NWFETs is also investigated. The extent to which the normalized Rsd in n-type NWFETs increases as dNW decreases is greater than in p-type NWFETs. This difference is verified using a simulation tool focusing on the extension region. The extended gate region is observed to be where the surface roughness scattering increases resistivity. The proportion of charges near the surface in this extended gate region of n-type NWFETs becomes greater than in p-type NWFETs as dNW decreases. The difference in the proportion of surface charges between n- and p-type NWFETs with 7, 9, and 12 nm dNW is 5.8%, 4.6%, and 1.0%, respectively. This is because volume inversion caused by the quantum confinement effect in p-type NWFETs becomes significant compared with the n-type NWFETs as dNW decreases.