Current Source Model of Combinational Logic Gates for Accurate Gate-Level Timing Analysis

Abstract

Static timing analysis (STA) is a design process to verify the satisfaction of timing constraints imposed on digital systems, and it is one of essential design verification steps for very large scale integration (VLSI) designs. For static timing analysis, it is conventional to model the delays of CMOS logic gates and the delays of interconnects separately, which are used to calculate the signal propagation delays of the system logic paths. As a means to compute the interconnect delay, PRIMA (Passive Reduced-order Interconnect Macromodeling Algorithm) or similar techniques are used to generate stable and passive reduced-order models of the interconnect. For CMOS logic gates, delay modeling is more complicated because of the nonlinearity associated with the CMOS transistors. There are many delay models proposed for CMOS logic gates. Most conventional delay models for CMOS logic gates are based on the lookup tables (LUTs) which store gate delay and output slew values as a function of the input slew and an effective load capacitance values. These models are fast and intuitive, and had been applied to practical STA for a long time. However, as the CMOS design goes into the deep sub-micron (DSM) technologies, the limitations of these models become obvious. The limitations are coming from many factors. Firstly, these models represent the input voltage waveforms as ramp inputs. Since the waveforms in DSM can be quite noisy due to some factors such as crosstalk noise and IR drop, simplification of the waveforms can lead to large gate delay errors. Secondly, the nonlinear capacitive load of a logic gate is approximated by a linear capacitance in these models. This approximation can be inaccurate when the gate drives a complex load. Therefore, it is desirable to have a more accurate model of logic gates for timing analysis, which can consider the input waveforms of various shapes and be independent of the load capacitance. The current source model (CSM) has been considered as a promising candidate which can address the above limitations of existing gate delay models. CSM is an equivalent macro model of a logic gate, which can handle arbitrary input voltage waveforms. CSM can provide high accuracy which is close to that of circuit simulation. Like the traditional LUT-based logic gate models, CSM is based on LUTs. However, unlike the traditional models which construct the LUTs of gate delays and output slews with respect to input slews and the effective load capacitances, CSM builds the LUTs of model parameters such as current sources and output capacitances as a function of node voltages. Since CSM depends on the node voltages only, it is independent of the load capacitance. Moreover, CSM can consider not only the single-input switching (SIS) cases but also the multiple-input switching (MIS) cases. This is a very useful feature if it is used for circuit analysis. Since the first CSM was proposed in 2003, CSMs have been developed into various forms. The existing CSMs can be accurate for a single-stage combinational logic gate, however, most of them suffer from large delay errors for multiple-stages of combinational logic circuits. Since the CSM of a multiple-stage combinational logic circuit is obtained by cascading single-stage CSMs, the large delay errors in the multiple stages was supposed to result from the inaccuracy at the input nodes of the existing CSMs. This thesis presents an extended CSM, which can provide high accuracy for single-stage and multiple-stage combinational logic circuits. The proposed CSM is based on an existing CSM which consists of voltage-controlled current source at the output node, input/output capacitances, and Miller capacitance between each input and output. And, in order to improve the modeling accuracy, we added a calibration capacitance and a current source at each input node. The calibration capacitance was added to compensate for the capacitance not characterized at the input node. The current source was added at each input node for the consideration of the gate leakage current. For the proposed CSM, a new characterization process of logic gates is described. The performance of the proposed CSM was evaluated through the experiments which considered SIS and MIS cases using saturated ramps and noisy waveforms as inputs. Experimental results indicated that the proposed CSM outperformed the benchmark CSMs in terms of average root-mean-square voltage error and average 50%-to-50% gate delay error. The proposed CSM can be used for accurate gate-level timing analysis and is a promising modeling candidate to be used for gate-level circuit analysis.