A Study on Frequency Synthesizer PLL for Low-Power Sensor Platform

Abstract

This thesis presents a fast-lock 2.4GHz fractional-N phase-locked loop (PLL) for ultra-low-power applications. To minimize power consumed by all the other circuits except for the main oscillator, we propose a master-slave PLL structure where a low-frequency master PLL is followed by a slave injection-locked oscillator operating at high-frequency. A frequency-error compensation circuit is also implemented in the slave oscillator to eliminate possible drift in the free-running frequency. With a fractional-N coarse-lock unit in the master PLL and a fine frequency initialization unit in the slave oscillator, the PLL supports two fast-lock modes – 1) start-up locking from deep power down mode and 2) instantaneous relocking from standby mode. The implemented PLL in 65nm CMOS consumes 250μW from 0.8V supply, demonstrating a power efficiency of 0.102mW/GHz. The PLL performs the two fast-lock operations with lock times of less than 22μs from deep power down and 1μs from standby, respectively.