A Study on Drain Voltage Ringing and Gate- Source Voltage Spike Phenomenon in Half Bridge Configuration Using SiC MOSFET

Abstract

While SiC MOSFET can be operated under high switching frequency and high temperature with very low power losses, one of the key challenges for SiC MOSFET is the electromagnetic interference (EMI) caused by steep switching transients and continuous switching ringing. Compared to Si MOSFET, the higher rate of SiC MOSFET drain current variation introduces worse EMI problems. SiC MOSFET has low on-state resistance and can work on high switching frequency, high voltage and some other tough conditions with less temperature drift, which could provide the significant improvement of power density in power converters as. However, for the bridge circuit, high dv/dt during fast switching transient of one MOSFET will amplify the negative influence of parasitic components and produce significant voltage spikes on the complementary MOSFET, which will threaten its safe operation. To reduce EMI generated from the switching ringing, this paper investigates the causes of switching ringing and voltage spike by considering the combined impact of parasitic inductances, capacitances, and low circuit loop resistance. In addition, accurate mathematical expressions are established to explain the ringing behavior and quantitative analysis is carried out to investigate the relationship between the switching transient and gate drive voltage. An analysis is presented in this paper based on the simulation results.