A Study on RF Noise Modeling and Device Design for Multi-gate FETs

Abstract

The double-gate junctionless MOSFET is one of the promising candidates beyond the 22-nm node due to its excellent gate controllability and the enhanced carrier-transport properties. Moreover without junctions between the source/drain and the channel, the fabrication process of double-gate junctionless MOSFET is much easier and simpler. It is crucial to develop the physics-based noise model which can accurately predict the thermal noise of JL MOSFETs for the CMOS technologies for low power, low noise RF applications. An improved DC model for double-gate junctionless pMOSFETs by including field-dependent mobility and doping-dependent diffusivity is proposed using a modified Einstein’s relation for heavily doped semiconductors. The suggested model is calibrated with experimental data in all regions of operation, from deep depletion to accumulation and from linear to saturated regimes. Based on the accurate DC model, new noise model has been demonstrated for all bias regimes. The calculated results for the channel thermal noise, the induced gate noise, and their correlated noise as a function of biasing conditions can provide physical insights on the noise properties of 18 nm double-gate junctionless pMOSFETs. This analytical thermal noise model is expected to help in designing and fabricating junctionless FETs for RF applications. Also, silicon bulk fin field-effect transistors (FinFET) are recognized as a promising candidate for sub-14 nm technology node due to their better electrostatic and short-channel effect immunity than the conventional planar MOSFETs. However, practical challenges still exist for these FinFETs to obtain better DC and AC performance. Therefore, a three-dimensional TCAD analysis of FinFETs is essential to optimize the best design, performance, and manufacturability options for the next-generation technology node without high cost investment. Finally, the effects of fin pitch and fin height on parasitic resistances and capacitances are systematically investigated to achieve the lower RC delay, which is an adequate metric of AC behavior of FinFETs, for Si bulk n/pFinFETs in SOC applications. The RC delays are directly extracted from the fully-calibrated TCAD I-V/C-V simulation results and quantitatively analyzed using parasitic capacitance components including a middle-of-the line (MOL) configuration up to Metal 1. When the fin pitch increase, the RC delay increases due to larger Cgg. On the other hand, the RC delay mostly decreases due to higher on-current as the fin height increases. The RC delay with different power supply voltages (VDD = 0.55 and 0.75 V) is also analyzed with the VDD scaling. The FinFET with selective deposition is suggested to improve RC delay about 7%.