Impact of geometrical parameters on the electrical performance of network-channel polycrystalline silicon thin-film transistors

Abstract

The effects of geometrical parameters on the electrical characteristics of network-channel low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) were investigated. The grain boundary and interface trap densities were also extracted using parameters such as hole-to-hole distance, hole-branch top width, effective channel width, and area filling factor (A(F)). It was found that the electrical characteristics were largely dependent on A(F), mainly owing to reduced trap densities. However, excessive hole formation in the network-channel structure was found to increase channel resistance and decrease drain current. These results suggest that, for a given footprint device area, denser hole patterns are preferred for achieving better electrical characteristics in novel network-channel LTPS TFTs. (C) 2018 The Japan Society of Applied Physics